table of Contents
-  The hierarchical structure of the memory
-  Classification of memory
-  SRAM
-  DRAM
-  Memory system design
-  Memory expansion design (emphasis)
-  Chip selection signal generation (decoding circuit) (emphasis)
Here we choose SRAM and DRAM
Static random access memory (SRAM): The
so-called "static" means that the data stored in this kind of memory can be kept constantly as long as it is powered on.
When the power supply stops, the data stored in the SRAM will still disappear (called volatile memory), which is different from the ROM or flash memory that can store data after a power failure.
Storage matrix, which determines the arrangement of storage units in the memory. There are two types of word structure and bit structure.
Address decoder, used to select storage units. There are two types of linear decoding and compound decoding. Compound decoding is usually
used. Control logic and three-state data buffer, control CS, WR, RD signals
Take 6116 (2K x 8) as an example:
2K : Represents the number of memory cells inside the chip, this number determines the number of memory chip address lines .
8 : Indicates the number of bits of information stored in each memory cell of the chip. This number determines the number of data lines of the memory chip .
The pin numbers are as follows:
Note: The address and control BUS point to the memory in one direction, and the data BUS is two-way.
The address lines of DRAM are multiplexed, that is, the address lines are divided into two parts: row address and column address. When accessing the memory cell, the row address strobe signal RAS sends the row address to the row address latch; the column address strobe signal CAS sends the column address to the column address latch
between CPU and DRAM The information exchange is completed by the DRAM controller.
Questions to be considered:
1. Bus load capacity
2. Coordination between CPU timing and memory access speed
3. Memory chip selection and number
4. On-chip addressing and inter-chip addressing address line allocation
5. Decoding circuit selection ( Linear decoding, full decoding, partial decoding)
6. Connection of data line and control line
Bit expansion refers to the expansion of the word length with multiple memory devices. One address controls multiple memory chips at the same time.
When performing bit expansion, the address lines and control lines of all chips in the module are interconnected to form the address lines and control lines of the entire module, and the data lines of each chip are aligned (bit line expansion) to form the data line (8bit width) of the entire module.
Why do I need bit extensions?
In a microcomputer system, the memory is composed of bytes, and
when the word length of the selected memory chip is less than 8 bits , the memory subsystem circuit required by the system must be expanded by using such a memory chip, that is,
Use several memory chips together to increase the storage word length. For example, in the figure above, two 4 bits form an 8 bit. So it is called "bit extension".
Word expansion refers to increasing the number of words in the memory.
When performing word expansion, the address lines, control lines and data lines of all chips in the module are interconnected to form the lower address lines, control lines and data lines of the entire module, and the upper address lines (extended word lines) of the CPU are used for decoding To form a selection line for each chip-chip selection line
1. 1. carry out bit expansion of the chip grouping to achieve byte addressing;
2. 2. design the chip selection of a chip set to carry out word expansion to meet the capacity requirements;
Except for addresses on-chip of the memory chip, other address buses of the CPU bus participate in the chip-select address decoding of the chip.
memory chip only occupies an area in the entire storage space, and a unique address is used to access the on-chip unit of the memory chip.
Example: In the microcomputer application system composed of 8088CPU working in the maximum mode, the
SRAM circuit of 8KB is expanded and designed , and the SRAM chip is Intel6264. If the starting address allocated to the SRAM is 62000H~
63FFFH, the chip select signal (CS1) is active low. Please use the full address decoding method to design the
chip select signal formation circuit of the SRAM memory.
1. Intel 6264
8K 8-bit SRAM
2. 8K 8 bits: 8KB, so only 1 piece of 6264 is needed, no need to expand
3. The address bus of 8086/8088CPU is 20 bits , the addressing range of 8086/8088CPU is 1MB ; 8086 has 16 data lines and 20 Root address line, it can handle both 16-bit data and 8-bit data. The addressable memory space is 1MB.
4. There are 13 address lines on the 6264 chip: A0~A12, so the lower 13 bits of the CPU bus are directly connected to the on-chip address pins as on-chip addressing to select specific units on the chip.
5. Due to the full decoding method, the upper 7 bits of the CPU, A19~A13, all participate in the decoding. And the number of chips is 1MB/8KB=128 pieces. So there are 128 chip select addresses. 2^7=128.
62000H/2000H=49 (10000H=8*2000H) converted to binary: 0110001
6. The chip select signal is active at low level, so in the address decoding design, if a gate circuit is used, pay attention to: A19 ~A13 All 1s are logically AND, and all 0s are logically ORed.
7. The system bus IO/M' also participates in decoding.
Summary: ...I feel that there are quite a lot of steps, but if you follow this process once, it will be very simple when you do it the second time.
Also called local address decoding. The chip select signal is not generated by the decoding of all address lines in the address line that are not on the memory, but only part of the high-order address lines are sent to the decoding circuit to generate the chip select signal.
Features: Some high-order address lines are omitted and do not participate in address decoding, which simplifies the address decoding circuit, but the address space overlaps.
For example, in a microcomputer system composed of 8088 CPU, the memory chip adopts a 6264 chip with a capacity of 8KB. When designing the address decoding, the address line A19 did not participate in the decoding, and only the 6 address lines A13-A18 participated in the decoding. At this time, each block of 6264 will occupy two 8KB memory spaces. In other words, the memory space has overlapped, and the overlap is shown in Figure 6.23. It can be seen from the figure that the 6264 chip connected to the lowest 8KB address area of the memory space actually occupies the memory address space: 00000H 01FFFH, 80000H 81FFFH. It occupies two 8KB of memory space. It can be deduced by analogy. If two high-order address lines do not participate in address decoding, then 4 storage spaces will overlap; if three high-order address lines do not participate in address decoding, 8 overlap spaces will be generated. The number of overlapping spaces satisfies the following relationship: the number of overlapping spaces = 2", where n is the upper address line that does not participate in address decoding.
Example: In a microcomputer application system composed of 8088 CPU working in a minimal way, the SRAM circuit of 8KB is expanded and designed, and the SRAM chip is Intel6264. If the address range allocated to the SRAM is 00000H~0FFFFH, the chip select signal (CS) is active low. Please use the partial address decoding method to design the chip selection signal forming circuit of the SRAM memory.
1. The capacity of 6264 is 8KB, but 00000H0FFFFH is 64KB, so there are 64KB/8KB=8 in the overlapping area, and 2<sup>3=8, so the three upper address lines are not decoded, such as A15A13
2. IO/M'=0 participate in decoding
Line selection method: select one of the higher address lines except the on-chip addressing of the memory chip as the chip selection signal of the memory chip.
Since the chip select address line can only have one bit valid for each addressing, and multiple bits are not allowed to be valid at the same time, this ensures that only one chip or one chip set is selected each time.
Advantages: No additional logic circuit is required to select the chip, and the aunt's circuit is simple.
Disadvantages: The address space is divided into mutually isolated areas, and there are many address overlapping areas, which cannot make full use of the system's memory space.
All address lines of the system should be involved in decoding The low-segment address line should be directly connected to the module to address the unit in the module; After the middle address line is decoded, a chip select signal is generated to distinguish different modules; The upper address line can be used as an effective enable control for the chip select signal; Copy code
Is not involved in decoding the address signal end, and cause discontinuous overlapping address spaces duplicated code
The circuit structure is simple, but the system must ensure that the address lines participating in the chip selection cannot be active at the same time; The same as the partial decoding method, because there are address signals that do not participate in the decoding, there are also the problems of address overlap and discontinuity Copy code
1. Determine the location of the memory in the entire addressing space according to the actual memory capacity in the system.
2. Draw the address allocation map and address allocation table
according to the capacity of the selected memory chip. 3. Determine the decoding based on the address allocation map or allocation table Method and draw the corresponding address bitmap
4. Select the appropriate period and draw the decoding circuit
The address bus of a certain microcomputer system is 16 bits, the actual memory capacity is 16KB, and the ROM area and RAM area each occupy 8KB. Among them, ROM uses 2KB EPROM, RAM uses 1KB RAM, try to design the decoding circuit.
1. The maximum addressing space of this system is 64KB, assuming that the actual memory occupies a minimum of 16KB of storage space, that is, the address is 0000H3FFFH. Among them, 0000H1FFFH is the EPROM area, and 2000H~3FFFH is the RAM area.
2. The capacity of the memory chip used, FIG address allocation can be drawn; address allocation table
for each sub-area of ROM is 2KB = 2 ^ 11, address lines 11 as required chip addressing: A0 ~ A10;
for For RAM, each sub-area is 1KB=2^10, and a 10-bit address line is required for on-chip addressing: A0~A9;
using 3-8 decoders, the first four points to four ROMs, and the last four add one A10 constitutes a secondary decoding, pointing to 8 pieces of RAM;
example question 1: In a certain 8088 microprocessor system, 8 pieces of 6264 are needed to form a 64KB memory. The address is allocated in the memory space of 0000H~0FFFFH, the address decoding adopts the full decoding method, and 74LS138 is used as the decoder. Please draw the memory decoding circuit.
1. There are 13 address lines on the 6264 chip: A0~A12, so the lower 13 bits of the CPU bus are directly connected to the on-chip address pins as on-chip addressing to select specific units on the chip.
2. Due to the full decoding method, the upper 7 bits of the CPU, A19~A13, all participate in the decoding. And the number of chips is 8 pieces.
Here we just use A13~A15 as the input of the decoder, so there are exactly 8 outputs. A16 to A19 are used as strobe signal 3, all 0.
Example: Using 74LS688 to design a decoding circuit, the output terminal (P=Q)' is used as the CS chip selection signal of Intel 62128 SRAM, and the address range allocated to Intel 62128 is 74000H~77FFFH. Draw the decoding circuit of 8088 CPU working in maximum mode.
Convert 74000H into binary: 0111 0100, 0000 0000 0000
77FFFH into binary: 0111 0111, 1111 1111 1111.
Observe that the first 6 digits are the same, so that you can locate a large range and determine Q The value of is: 101110 (from low to high)
So the result is as follows:
If you need to change the address of the memory chip, you only need to change the switch on the Q side. So this structure can bring convenience for changing the memory address.
If you do not need to change the address, you can directly specify the code of the Q side.
"Microcomputer Principles and Interface Technology. Lou Shuntian Edition"